The present invention relates to a method of extracting timing characteristics from transistor circuit data in modularity design products of a CPU core and others and extracted timing characteristics are used for timing constraints when the timing verification of a circuit including an extracted module, logic synthesis or timing-driven layout is performed. Particularly, as the condition fit for a timing rule of a module is included in timing characteristics when timing verification is performed by simulation, verification free of a pseudo error is enabled. The present invention also relates to the structure of a timing characteristic library, a storage medium storing it and an LSI designing method using it.
The age of a large-scale one-chip system is coming and it is being essential to provide system LSI utilizing already designed data in a short term so as to enhance the competitive strength of a chip and a system. Particularly recently, design products or the design of system LSI utilizing intellectual properties (IP) rapidly increases. For example, in the design of an application specific integrated circuit (ASIC) reusing modularity design products of a CPU core and others, the manufacturer of ASIC provides a module to a client such as a system house and the client designs adds a logic proper to the client to the module and designs ASIC. At this time, it is not enough to provide only the description of a logical function to the client. Because the timing verification of the whole chip is required to be executed. In this case, a CPU core viewed from the side of a client is a black box and the timing verification of the whole chip is impossible without timing characteristics in an interface of a CPU core. To provide timing characteristics to a client, characteristics are required to be extracted from a module, however, heretofore, extraction work depended upon manual labor. Therefore, considerable man-hours were required and simultaneously, there was always fear that an error might be included in a timing extraction result.
Then, the object of the present invention is to extract timing characteristics from the layout data of a module. As for the present invention, for a method of extracting timing characteristics, a method of extracting timing characteristics every cell and utilizing the result of the extraction was also examined.
For a method using prior art, there is Japanese published unexamined patent application No. Hei 4-316166 disclosing a timing characteristics extracting tool at a cell level and others. In these methods, the data of a transistor circuit is input, the simulation of the whole circuit is automatically executed and timing characteristics are extracted, however, as the scale of a dealt circuit is a level of a cell, a circuit composed of approximately a few hundred transistors is dealt and a large-scale transistor circuit of a few MB cannot be dealt. Difference between a large-scale transistor circuit and a circuit at a cell level will be described below.
(1) At a cell level, it may be also thought that a cell of a sequential circuit is equivalent to a bistable circuit (a flip-flop (FF)) and the effect of another circuit between the terminal of a cell and a bistable circuit is not required to be considered. A case that plural bistable circuits have an effect upon timing is also not required to be considered.
(2) At a cell level, as a circuit is composed of a few hundred transistors, timing characteristics can be extracted even if the whole circuit is simulated. In the meantime, to extract the timing characteristics of the whole large-scale circuit in simulation, considerable processing time is required.
(3) At a cell level, the extraction of the timing characteristics of a complicated circuit acquired by combining bistable circuits is not a target. A large-scale circuit includes a complicated sequential circuit such as a divided clock generating circuit and such a circuit is also required to be dealt.
In the present invention, a method of realizing the extraction of timing characteristics of a large-scale circuit is provided in view of the above difference.
As in prior art, a method of extracting timing characteristics at the level of a small-scale cell is dealt, the prior art itself cannot be applied to a large-scale circuit as described in above (1) to (3). There are the following three objects in relation to dealing a large-scale transistor circuit.
(1) To provide a method of modeling and processing the definition of timing characteristics at a terminal even if plural bistable circuits are included in addition to a circuit except a bistable circuit.
(2) To provide a method of modeling and processing timing characteristics the processing time of which is in a range of actual use even if a transistor circuit of a few MB is dealt.
(3) To provide a method of dealing in case a complicated circuit is included.
Means to achieve the above three objects will be described below.
First, a modeling method to achieve the objects (1) and (2) will be described and next, a processing method will be described.
(1) Modeling Method
The target of a module is a synchronized circuit shown in FIG. 3. For timing characteristics, there are two types of delay of output and a timing rule of input (setup time/hold time). As a target circuit is a synchronized circuit, timing is based upon a clock. That is, output delay means delay of output based upon time when a clock varies and a timing rule means is a generic term of constraints on the setup time or the hold time of input in relation to a clock.
The timing and a circuit that determines timing of a synchronized circuit are as follows.
In the case of output delay, as shown in FIG. 3, the last bistable circuit (FF) 35 finally having an effect upon output functions as a basic circuit that determines timing. That is, time until the last bistable circuit 35 is activated according to a clock 311 and the change of the output of the bistable circuit is propagated to output 313 is output delay. Therefore, associated circuits are circuits on a path from a clock to output via the last bistable circuit. As plural paths may exist as to the above path, the delay value of a path having the maximum delay value that has the worst effect upon other circuits is output delay in consideration of all circuits on these paths.
In the case of a timing rule, as shown in FIG. 3, a first bistable circuit 34 which input 312 first reaches is a basic circuit that determines timing. That is, if input is unstable since before the setup time of time when a clock varies until after a hold time, the output of the first bistable circuit varies and desired output cannot be acquired. In this modeling method, the above timing rule (setup time and hold time) is not directly acquired including a bistable circuit but is acquired by adding or subtracting the skew of delay from a clock to a bistable circuit ck 32 and delay from input to a bistable circuit d 33 to/from a timing parameter of a bistable circuit. FIG. 4 shows the above calculating method. Further, other circuits forms a long path between a bistable circuit and an input/clock terminal and even if a clock and input vary at a terminal, the variation is not always propagated to a bistable circuit. Therefore, as shown in FIG. 4, a rule is checked by inputting a condition fit for the rule to a timing rule and testing whether variation is propagated or not. Unless the above test is performed, a signal used in another circuit is also checked in verification by simulation shown in FIG. 18 and a pseudo error frequently occurs.
Based upon the above modeled timing rule, if plural first bistable circuits exist, the maximum value of the timing parameters of the plural first bistable circuits is adopted as shown in FIG. 4 and the conditions fit for the rule of all the first bistable circuits are ORed.
(2) Processing Method
To acquire a model described in above (1), a method shown in FIG. 1 is adopted.
First, transistor circuit data 102 is input and a gate and a bistable circuit are reconstructed in a step 11. Afterward, a first bistable circuit and a last bistable circuit which the above data respectively first reaches from an input terminal and an output terminal are searched and circuits from each terminal to each bistable circuit are recognized as associated circuits in a step 12.
As described in the problem (2), as it takes much processing time to measure delay in the simulation of the whole large-scale transistor circuit, an effective path from each bistable circuit to input/output is searched and a path 104 the delay of which is to be measured is input to a high-speed static delay measuring tool in a step 13. Hereby, as a path which is logically impossible is prevented from being included in paths the delay of which are measured in the static delay measuring tool, the above step is necessary. Simultaneously, a condition (an activating condition 105) for input/a clock to propagate change to the first bistable circuit is generated in a step 14. A timing characteristic library 108 is generated based upon the delay 106 measured in measuring delay 15, the activating condition 104 and the bistable timing rule 107 according to the modeling method acquired in above (1) in a step 16.
For means for solving the problem described in the problem (3), there are the recognizing method in the step 12 and the method of generating an activating condition in the step 14. The main problem is how to deal a divided clock generating circuit and an element except a combinational circuit. The above main problem will be described in best embodiments for embodying the present invention in detail.